1. Technical Field
The present disclosure relates to a method for forming an integrated circuit chip, and more specifically a method for forming an integrated circuit chip having its front surface and its rear surface electrically connected by means of a via crossing the wafer.
2. Discussion of the Related Art
To improve the compactness and the performance of integrated circuits, it is desired to transfer connections to components manufactured on the front surface of a semiconductor wafer (or semiconductor substrate) to the rear surface of the wafer. To achieve this, vias forming the wafer, currently designated in the art as TSVs (“Through Substrate Vias”), should be formed. Such vias comprise one or several materials which are good electric and/or heat conductors.
To limit the thickness of the substrate to be crossed, the forming of integrated circuits comprising TSV-type vias generally results in the manipulation of semiconductor wafers of very small thickness. This generates a high mechanical stress in the wafer and in the integrated circuit. Further, to limit the loss of useful area on the side of the wafer where the components are formed, it is desired to form vias having as small a cross-section as possible. It is thus desired to form vias having a high form factor, the form factor of a via being defined as the ratio of the depth of the via to the width of this via.
Generally, presently-used technologies enable to easily manufacture vias having a form factor ranging between 1 and 10. For a thin wafer, having a thickness on the order of 80 μm, the smallest via width that can be easily manufactured thus is approximately 8 μm. For technologies where the dimensions of elementary active components are smaller than one micrometer, or even than one tenth of a micrometer, such widths are very large as compared with the dimensions of the manufactured components, mainly transistors. A portion of the surface of the semiconductor wafer normally dedicated to component manufacturing is thus sacrificed for the manufacturing of through vias. Thus, the provision of vias may result in a decrease in the density of components per surface area unit.
To decrease the width of through vias, the wafer should thus be thinned as much as possible. Wafers of large diameter, for example, wafers having a 300-mm diameter, which generally have an initial thickness approximately ranging from 700 to 800 μm, become brittle and difficult to manipulate after a thinning. The front surface of the wafer is thus glued to a temporary handle, that is, to another thicker wafer, after which the wafer is thinned. Openings are then formed from the new rear surface of the wafer, after which the walls and the bottom of the openings are covered with a layer of a conductive material. To obtain a conformal deposition of the conductive material on the walls and the bottom of the openings, high temperatures should be used. Presently, glues used for gluing of the wafer on the temporary handle do not stand well temperatures greater than approximately 250° C. A disadvantage of such methods is the fact that they may be limited to simplifying manufacture of vias having a limited form factor, generally ranging between 1 and 3.
According to another known method, to improve the form factor of the vias, the vias are formed before the temporary gluing of the wafer on a handle, and before thinning of the wafer. However, due to the desired final thickness of the wafer, generally on the order of 80 μm, a disadvantage of such a method is the expensive filling of the vias.
Another disadvantage of the above-described methods is that, once the handle has been removed, the wafer is brittle. The wafer is then difficult to manipulate in subsequent encapsulation steps. By such methods, it is thus difficult to obtain wafers having a thickness smaller than approximately 80 μm, and thus through vias having a width smaller than 8 μm.
There thus is a need for a method enabling to transfer connections to components manufactured on the front surface of a semiconductor wafer to the rear surface of the wafer by vias having the smallest width possible.